The accelerated software data plane has a powerful line-rate packet processing capability and flexible programmability at 100 Gbps and higher throughput.

We propose an FPGA SmartNIC-based reconfigurable accelerator to offload some of the operation-intensive packet processing functions from the software data plane to reconfigurable hardware, thus improving the overall data plane performance while retaining flexibility. Therefore, hybrid implementation where a hardware device is adopted as the accelerator is proposed to balance the performance and flexibility. However, completely implementing the data plane on hardware weakens the flexibility. With sharp increases in network capacity, CPU-based packet processing is overwhelmed. The software data plane of SDN is commonly implemented on a commercial off-the-shelf (COTS) server, executing an entire processing logic on a commodity CPU. To support the flexibility of the data plane, the software implementation approach is adopted. The architecture of the SDN data plane is also evolving. Software-defined networking (SDN) has attracted much attention since it was proposed.

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